ELECTRICAL AND COMPUTER ENGINEERING
6730C Boelter HallEmail: firstname.lastname@example.org
Phone: (310) 825-1376
RESEARCH AND INTERESTS
- Design-technology co-optimization and physical design
- Emerging memory systems and reliability-aware computer architectures
- Lightweight machine learning systems
- Chiplet-based systems and waferscale computing
- W. Romaszkan, T. Li, and P. Gupta, “SASCHA – Sparsity-Aware Stochastic Computing Hardware Architecture for Neural Network Acceleration,” in ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022. (best paper nomination)
- S. Li and P. Gupta, “Bit-serial Weight Pools: Compression and Arbitary Precision Execution of Neural Networks on Resource Constrained Processors,” in Conference on Machine Learning and Systems (MLSys), 2022
- I. Alam and P. Gupta, “COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors,” in IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2022
- S. Pal, J. Liu, I. Alam, N. Cebry, H. Suhail, S. Bu, S. S. Iyer, S. Pamarti, R. Kumar, and P. Gupta, “Designing a 2048-Chiplet, 14336-Core Waferscale Processor,” in Proc. ACM/IEEE Design Automation Conference (DAC), 2021.
- S. Pal, D. Petrisko, M. Tomei, S. S. Iyer, P. Gupta, and R. Kumar, “Architecting Waferscale Processors – A GPU Case Study,” in IEEE International Symposium on High-Performance Computer Architecture (HPCA), 2019, pp. 250-263.
- W.-C. Wang, C.Zhao and P. Gupta, “Assessing Layout Density Benefits of Vertical Channel Devices,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2018.
- S. Wang, H. Lee, C. Grezes, K. P. Amiri, K. L. Wang, and P. Gupta, “Adaptive MRAM Write and Read with MTJ Variation Monitor,” Transactions on Emerging Topics in Computing, 2018.
- M. Gottscho, I. Alam, C. Schoeny, L. Dolecek, and P. Gupta, “Low-Cost Memory Fault Tolerance for IoT Devices,” ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), published in ESWEEK special issue of the ACM Transactions on Embedded Computing Systems (TECS), 2017. (best paper award)
- L. Lai, V. Chandra, R. Aitken, and P. Gupta, “SlackProbe: A Flexible and Efficient In Situ Timing Slack Monitoring Methodology,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 1168-1179, Aug 2014.
- A.A. Kagalwalla and P. Gupta, “Comprehensive defect avoidance framework for mitigating extreme ultraviolet mask defects,” SPIE Journal of Micro/Nanolithography, MEMS and MOEMS (JM3), vol. 13, no. 4, p. 043005, 2014.
- R.S. Ghaida and P. Gupta, “DRE: a Framework for Early Co-Evaluation of Design Rules, Technology Choices, and Layout Methodologies,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012.
- P.Gupta, Y. Agarwal, L. Dolecek, N. Dutt, R. K. Gupta, R. Kumar, S. Mitra, A. N. T. S. Rosing, M. B. Srivastava, S. Swanson, and D. Sylvester, “Underdesigned and opportunistic computing in presence of hardware variability,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2012. Keynote Paper.
IN THE NEWS
- B. Tech, Electrical Engineering, Indian Institute of Technology, 2000
- Ph.D., Computer Engineering, University of California, San Diego, 2007
AWARDS AND RECOGNITION
- 2021, IEEE Fellow
- 2012, IBM Faculty Award
- 2010, ACM/SIGDA Outstanding New Faculty Award
- 2009, SRC Inventor Recognition Award
- 2009, NSF Faculty Early Career Development (CAREER) Award
- 2007, European Design Automation Association (EDAA) Outstanding Dissertation Award
- ECE100: Electrical and Electronic Circuits
- ECE10: Circuit Theory I
- ECEM116C: Computer Systems Architecture
- ECE201A: VLSI Design Automation
- ECE201D: Design in Nanoscale Technologies