ELECTRICAL AND COMPUTER ENGINEERING
56-147E Engr. IVEmail: firstname.lastname@example.org
Phone: (310) 825-8656
RESEARCH AND INTERESTS
- Implantable neuromodulation systems
- Domain-specific compute architectures
- Design methodologies
- D. Rozgić, et al., "A 0.338cm3, Artifact-Free, 64-Contact Neuromodulation Platform for Simultaneous Stimulation and Sensing," IEEE Trans. Biomedical Circuits and Systems, vol. 13, no. 1, pp. 38-55, Jan. 2019.
- H. Chandrakumar, D. Marković, “A 15.2-ENOB 5kHz-BW 4.5µW Chopped CT ΔΣ-ADC for Artifact-Tolerant Neural Recording Front-Ends,” IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3470-3483, Nov. 2018.
- W. Jiang, V. Hokhikyan, H. Chandrakumar, V. Karkare, D. Marković, "A ±50-mV Linear-Input-Range VCO-Based Neural-Recording Front-End With Digital Nonlinearity Correction," IEEE Journal of Solid-State Circuits, vol. 52, no. 1, pp. 173-184, Jan. 2017.
- R. Dorrance and D. Marković, "A 190GFLOPS/W DSP for Energy‐Efficient Sparse‐BLAS in Embedded IoT," in Proc. IEEE Symp. VLSI Circuits (VLSI'16), June 2016.
- F. Ren and D. Marković, “A Configurable 12-to-237kS/s 12.8mW Sparse-Approximation Engine for Mobile Data Aggregation of Compressively-Sampled Physiological Signals,” IEEE J. Solid-State Circuits, vol. 51, no. 1, pp. 68-78, Jan. 2016.
- D. Rozgić and D. Marković, "A 0.78mW/cm2 Autonomous Thermoelectric Energy-Harvester for Biomedical Applications," in Proc. IEEE Symp. on VLSI Circuits (VLSI'15), June 2015, pp. 278-279.
- F-L Yuan, C.C. Wang, T-H Yu, D. Marković, “A Multi-Granularity FPGA with Hierarchical Interconnects for Efficient and Flexible Mobile Computing,” IEEE J. Solid-State Circuits, vol. 50, no. 1, pp. 137-149, Jan. 2015.
- V. Karkare, S. Gibson, and D. Marković, "A 75 µW, 16-channel Neural Spike Sorting Processor with Unsupervised Clustering," IEEE J. Solid-State Circuits, vol. 48, no. 9, pp. 2230-2238, Sep. 2013.
- C.-H. Yang, T.-H. Yu, D. Marković, "A 5.8mW 3GPP-LTE Compliant 8×8 MIMO Sphere Decoder Chip with Soft-Outputs," in Proc. Int. Symp. VLSI Circuits (VLSI), June 2010, pp. 209-210.
IN THE NEWS
- PhD, UC Berkeley (2006)
- MS, US Berkeley (2000)
- BS, University of Belgrade, Serbia (1998)
AWARDS AND RECOGNITION
- IEEE Fellow (Class of 2021)
- 2014, 2014 ISSCC Lewis Award for Outstanding Paper
- 2011, Associate Editor, IEEE Journal of Solid-State Circuits
- 2010, ISSCC Jack Raper Award for Outstanding Technology Directions (link)
- 2010, DAC/ISSCC Student Design Contest Winner
- 2009, NSF CAREER Award
- 2007, UC Berkeley David J. Sakrison Memorial Prize
- 2004, IEEE ISQED Best Paper Award (link)
- 2002, UC Berkeley CalVIEW CITRIS Award for excellence in distance education
- 2001, UC Berkeley CalVIEW Fellow Award for excellence in distance education
- ECE 115C, Digital Integrated Circuits
- ECE M216A, Design of VLSI Circuits and Systems
- ECE 216B, VLSI Signal Processing
- BME M260, Neuroengineering