Analog, RF, mixed-signal integrated circuit design, dual-standard RF transceivers, phase-locked systems and frequency synthesizers, A/D and D/A converters, high-speed data communication circuits

• Analysis and Design of Data Converters, Cambridge University Press, 2025.
• M. C. Snai, H. Razavi, P. K. Khanna and B. Razavi, " A 140-GHz 40-mW Receiver with LO Generation and Phase Shifting for Beamforming Applications," European Solid-State Electronics Research Conference, Sept. 2024.
• K. Tyagi and B. Razavi, " A 56-Gb/s 17-mW NRZ Receiver in 0.018 mm2," Symposium on VLSI Circuits Dig. Of Tech. Papers, June 2024.
• P. K. Khanna, Y. Zhao, M. Forghani and B. Razavi, " A Low-Power 28-GHz Beamforming Receiver with On-Chip LO Synthesis," European Solid-State Circuits Conference, Sept. 2023.
• M. Forghani, Y. Zhao, P. K. Khanna and B. Razavi, " A 112-Gb/s 58-mW PAM4 Transmitter in 28-nm CMOS Technology," Symposium on VLSI Circuits Dig. Of Tech. Papers, pp. 1-2, June 2023.
• M. Jara and B. Razavi, "A 6-bit 10-GS/s 17.6-mW CMOS ADC with 0.8-V supply," Proc. IEEE Custom Integrated Circuits Conference, April. 2023.
• K. Tyagi and B. Razavi, " Effect of ADC Clock Jitter on the Performance of PAM4 and PAM6 Receivers," IEEE International Symposium on Circuits and Systems, May 2023.
• M. Snai and B. Razavi, " Optimal Distribution of High-Speed Clocks on Transceiver Chips," IEEE International Symposium on Circuits and Systems, May 2022.
• Y. Zhao and B. Razavi, " Phase Noise Integration Limits for Jitter Calculation," IEEE International Symposium on Circuits and Systems, May 2022.
• M. Forghani and B. Razavi, " Circuit Bandwidth Requirements for NRZ and PAM4 Signals," IEEE International Symposium on Circuits and Systems, May 2022.
• Y. Zhao, O. Memioglu and B. Razavi, " A 56GHz 23mW Fractional-N PLL with 110fs Jitter," ISSCC Dig. Tech. Papers, pp. 1-3, Feb 2022.
• O. Memioglu, Y. Zhao and B. Razavi, " A 300GHz 52mW CMOS Receiver with On-Chip LO Generation," ISSCC Dig. Tech. Papers, pp. 1-3, Feb 2022.
• A. Manian and B. Razavi, “A 32-Gb/s 9.3-mW CMOS Equalizer with 0.73-V Supply,” Proc. IEEE Custom Integrated Circuits Conference, Sept. 2014.
• B. Razavi, “The Role of Translational Circuits in RF Receiver Design,” Proc. IEEE Custom Integrated Circuits Conference, Sept. 2014.
• S. Hwu and B. Razavi, “A Receiver Architecture for Intra-Band Carrier Aggregation,” Symposium on VLSI Circuits Dig. Of Tech. Papers, pp.142-143, June 2014.
• J.W. Jung and B. Razavi, “A 25Gb/s 5.8mW CMOS Equalizer,” ISSCC Dig. Tech. Papers, pp.44-46, Feb. 2014.
• J.W. Park and B. Razavi, “Channel Selection at RF Using Miller Bandpass Filters,” IEEE Journal of Solid-State Circuits, vol. 49, pp. 3063-3078, Dec. 2014.
• S. Hashemi and B. Razavi, “A 7.1 mW 1 GS/s ADC With 48 dB SNDR at Nyquist Rate,” IEEE Journal of Solid-State Circuits, vol. 49, pp. 1739-1750, Aug. 2014.
• H. Wei and B. Razavi, “An 8 Bit 4 GS/s 120 mW CMOS ADC,” IEEE Journal of Solid-State Circuits, vol. 49, pp. 1751-1761, Aug. 2014.
• S. Hashemi and B. Razavi, “Analysis of Metastability in Pipelined ADCs,” IEEE Journal of Solid-State Circuits, vol. 49, pp. 1198-1209, May. 2014.
• S.W. Chiang and B. Razavi, “A 10-Bit 800-MHz 19-mW CMOS ADC,” IEEE Journal of Solid-State Circuits, vol. 49, pp. 935-949, Apr. 2014.
• A. Homayoun and B. Razavi, “Relation Between Delay Line Phase Noise and Ring Oscillator Phase Noise,” IEEE Journal of Solid-State Circuits, vol. 49, pp. 384-391, Feb. 2014.

• 2023, Top author in 70-year history of ISSCC
• 2022, Top Two Prizes, IEEE Solid-State Circuits Society Design Contest, Kshitiz Tyagi and Matias Jara
• 2022, Darlington Best Paper Award (Jitter-Power Trade-Offs in PLLs), IEEE Transactions on Circuits and Systems
• 2022, IEEE Solid-State Circuits Society Innovative Education Award
• 2022, Fellow of National Academy of Inventors
• 2017, IEEE CAS John Choma Education Award
• 2017, Member of National Academy of Engineering
• 2016, Outstanding PhD Dissertation Award, Abishek Manian, EE Dept.
• 2015, Best Student Paper Award (with Abishek Manian), VLSI Circuits Symposium
• 2014, ASEE PSW Outstanding Teaching Award awarded by the American Society for Engineering Education, the citation reads, “For his superlative teaching and his seminal textbooks.”
• 2013, Best Paper Award in the IEEE Custom Integrated Circuits Conference H.Wei and B. Razavi, “An 8-Bit 4-GS/s 120-mW CMOS ADC,” Proc. IEEE Custom Integrated Circuits Conference, Sept. 2013.
• 2012, IEEE Donald O. Pederson Award “For his pioneering contributions to the design of high speed CMOS communication circuits”
• 2012, IEEE VLSI Circuits Symposium Best Student Paper Award J.W. Jung and B. Razavi, “A 25-Gb/s 5-mW CMOS CDR/Deserializer,” Symposium on VLSI Circuits Dig of Tech. Papers, pp.138-139, June 2012
• 2012, IEEE Custom Integrated Circuits Conference Best Invited Paper Award B. Razavi, “Problem of Timing Mismatch in Interleaved ADCs,” Proc. IEEE Custom Integrated Circuits Conference, Sept. 2012.
• 2009, IEEE Custom Integrated Circuits Conference Best Invited Paper Award B. Razavi, “Challenges in the Design of Cognitive Radios,” Proc. IEEE Custom Integrated Circuits Conference, pp. 391-398, Sept. 2009.
• 2007, UCLA Faculty Senate Teaching Award
• 2006, Lockheed Martin Excellence in Teaching
• 2003, IEEE Fellow
• 2001, McGraw-Hill First Edition of the Year for the book “Design of Analog CMOS Integrated Circuits,”
• 2001, ISSCC Beatrice Winner Award for Editorial Excellence J. Savoj and B. Razavi, “Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems,” Proc. Design Automation Conference, pp. 121-126, June 2001.
• 2001, IEEE Solid-State Circuits Conference Outstanding Student Paper Award L. Der and B. Razavi, “A 2-GHz CMOS Image-Reject Receiver with Sign-Sign LMS Calibration,” Dig. International Solid-State Circuits Conference, pp. 294-295, Feb 2001.
• 1998, IEEE Custom Integrated Circuits Conference Best Paper Award B. Razavi, “CMOS Technology Characterization for Analog and RF Design,” (Invited) Proc. of IEEE Custom Integrated Circuits Conference, pp. 23-30, May 1998.
• 1997, TRW Innovative Teaching Award
• 1997, ISSCC Best Panel Award
• 1994, IEEE European Solid-State Circuits Conference Best Paper Award B. Razavi, “A 100MHz 10-mW All-NPN Sample-and-Hold Circuit with 3-V Supply,” Proc. of European Solid-State Circuits Conference, pp. 192-195, Sept. 1994.
• 1994, ISSCC Beatrice Winner Award for Editorial Excellence B. Razavi and J. Sung, “A 6-GHz 60-mW BiCMOS Phase-Locked Loop with 2-V Supply,” Dig. of International Solid-State Circuits Conference, pp. 114-115, Feb. 1994.
• 1994, ISSCC Best Panel Award